Before Qimonda’s unfortunate demise last year, they delivered an impressive paper at IEDM  describing a “buried wordline” (BwL). Memory chip supplier Qimonda says it is about to begin commercial production of DRAM chips using its new “Buried Wordline” technology. Provided are a semiconductor device having a buried word line structure in which a gate electrode and a word line may be buried within a substrate to reduce.
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These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section.
Semiconductor memory devices including vertically oriented transistors and methods of manufacturing such devices. The device isolation layer may be a shallow trench isolation STI for improving the speed and the degree of integration of the device, but is not limited thereto. The buried word line may be formed by forming a word line layer on the substrate so as to bury the trench However, this is merely illustrative, and thus, the gate electrode layer and the buried word line are not limited to these materials.
Example embodiments provide a semiconductor device having a buried word line structure in which a gate electrode and a word line may be buried inside of a substrate, thereby reducing the height of the semiconductor device and the degradation of oxide layers due to the application of a TiN metal gate. When forming the lower buried word line with polysilicon using the atomic layer deposition method, a gas of a silicon source including one selected from the group consisting of SiH 4 gas, Si 2 H 6 gas, and Si 3 H 8 gas, or a combination thereof may be used.
‘Buried Wordline’ DRAM becomes reality | Electronics News
In addition, a description of forming layers within and on the gate using deposition and etching techniques is also well known to those skilled in the art, and thus, omitted. This application claims priority under 35 U. The foregoing is illustrative of example embodiments and is not to be burie as limiting thereof. The device may be otherwise oriented rotated 90 degrees or at other orientations and the spatially relative descriptors used herein interpreted accordingly.
As such, the deposition of the metal that forms the upper buried word line may be performed more easily. As such, there may be less leakage current. Hereinafter, the description overlapping with that described above will be omitted for the purpose of clarity.
Winbond Adopts Qimonda’s Buried Wordline Technology – Metal Gates Come to DRAMs | Siliconica
Example embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of example embodiments and intermediate structures. The upper buried word line may comprise a silicide.
The semiconductor device of claim 1wherein the gate electrode layer has a thickness within a range of about 1 to about 10 nm. An active region of a source and drain is formed in the substrate adjacent to both sides of the metal gate electrode The lower buried word line may be formed by recessing the polished first word line layer into the substrate Comments won’t automatically be posted to your social media accounts unless you select to share.
The first word line layer may then be polished using chemical mechanical polishing to expose the surface of the substrate Therefore, in the above structure, the semiconductor device having a height corresponding to the protruded portion of the metal gate electrode 20 is formed.
In example embodiments, forming the buried word line may include forming a lower buried word line in a lower region of the gate electrode layer and forming an upper buried word line in an upper region of the gate electrode layer, the upper buried word line being formed of a material different from that of the lower buried word line. Transistor having dual work function bruied gate electrode, method for manufacturing the same and electronic device having the same.
6F2 buried wordline DRAM cell for 40nm and beyond
Method of forming semiconductor device and semiconductor device wlrdline by the same. It will be understood that, although the terms first, second, third etc.
As such, the degradation of the oxide layer, which may be caused by the formation of the titanium nitride layer, may be reduced or prevented. The buried word line may comprise any one selected from the group consisting of tungsten Waluminum Alcupper Cumolybdenum Wordlinwtitanium Titantalum Taand ruthenium Ruor a combination thereof.
The top surface of the capping layer may be formed so as to not protrude beyond the surface of the substrate. The upper buried word line may be formed by forming a second word line layer not shown on the substrate so as to bury the trench including the lower buried word line Materials used to form the gate electrode layer will be described in detail below.
‘Buried Wordline’ DRAM becomes reality
The upper buried word line may be formed of any one of tungsten Waluminum Alcupper Buriesmolybdenum Motitanium Titantalum Taand ruthenium Ruor a combination thereof. As such, when the gate electrode and the word line are formed of only titanium nitride Tinthere may be an increase in leakage current.
Like reference numerals refer to like elements throughout. The trench may have a width within a range of about 10 to about nm.